The present application relates to systems, devices and methods for maskless material modification on or in substrates using charged particle beams; and more particularly to directly modifying material properties at precise locations as defined in a design layout database using multiple, matched charged particle beams, with the assistance of gas and/or photon injection, and/or of gas and/or photon process control, metrology and endpoint detection.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art.
FIG. 2A shows an example of a wafer 200 being scanned by multiple charged particle beams 204 emitted by respective miniature electrostatically-deflected beam columns 206. Individual columns 206 are able to target a portion 202 of the substrate surface 606 with their respectively emitted beams 204.
FIG. 2B shows an example of a wafer 200. Example die 208 size and column 206 center-to-center spacing 210 (column separation) are shown. A regular grid of columns 206 (columns 206 are shown via their center positions, represented here as plusses) can use different spacing 210 in different (generally, orthogonal) directions. Die 208 size and column separation 210 are not required to (and generally, will not) correspond. Column separation 210 generally corresponds to the “writing area” of corresponding columns 206. A column's 206 “writing area” is defined as the substrate area 202 targetable by a charged particle beam 204 emitted from the column 206, taking into account stage movement.
The multiple column 206 array comprises miniature (small enough to fit multiple columns in an array) charged particle beam columns 206 arranged in a regular grid. For example, column 206 arrays with center-to-center column spacing 210 of 30 mm×30 mm have been implemented, though other column spacings 210 (e.g., 24 mm×33 mm) can also be used.
A stripe is the portion of the wafer 200 surface that a charged particle beam can target while the stage is moving predominantly in a single direction, i.e., before the stage moves laterally and switches predominant directions to give the beam access to a different stripe. A “frame” is defined herein as the portion of the wafer surface that a beam can target at a given time, corresponding to the main-field deflection area at that time, as designated by the design layout database. A frame is typically designated to be rectangular, for convenience (e.g., to tile the writing area); and smaller than the furthest extent to which the beam can be deflected (e.g., to preserve beam targeting accuracy).
“1-D” refers to 1-D gridded design rule. In a 1-D layout, optical pattern design is restricted to lines running in a single direction, with features perpendicular to the 1-D optical design formed in a complementary lithography step known as “cutting”. The complementary step can be performed using a charged particle beam lithography tool comprising an array of columns 206—for example, electrostatically-controlled miniature electron beam columns 206. A 1-D layout is separated in the design layout database into a “line pattern” and a “cut pattern”. The design layout database contains the information needed by lithography tools to pattern one or more layers on a substrate 604. A line pattern generally comprises an array of unidirectional lines. Cut patterns generally comprise line-cuts and holes (“cut features”).
Generally, line patterns are written by an optical lithography system, which can be followed by other process steps to increase the density of lines on the substrate 604. Cut patterns are written by a complementary (generally higher-resolution) process, such as electron beam lithography. Use of electron beam lithography for this complementary process is also called complementary e-beam lithography, or CEBL. The combination of the line-forming process followed by line-cuts written with CEBL to pattern a substrate layer is called complementary lithography.
FIG. 2C shows an example of a prior art process for modifying material on (or in) a substrate 604 using ion implantation.
Typically, as shown in FIG. 2C, a design layout database is used to designate where on a substrate material should be modified 212 (e.g., to form transistor active areas through ion implantation). One or more optical masks are fabricated based on the design layout database 214 using a mask making tool 216. Fabrication of an optical mask set (multiple masks) typically takes weeks and costs millions of dollars at advanced process nodes.
“Blanket” deposition and etch (or other process) generally refers to deposition and etch (or other process) on the entire surface 606 of the substrate 604.
“Resist” refers herein to a class of materials used in substrate lithography. When a resist is deposited on a substrate 604 and exposed to an energy source corresponding to the type of resist (e.g., photons for a photoresist) in a chosen pattern, its chemical properties change (e.g., causing cross-linking between or dissociation of resist molecules) such that when the resist is developed (in ways similar to developing a photographic film), a portion of the resist corresponding to a positive or negative image of the pattern (depending on the type of resist) will remain, allowing the pattern to be expressed in the material underlying the resist, e.g., using etch steps. Portions of a positive tone resist which have been exposed to a corresponding energy source become soluble to and will be removed by a corresponding developer. Portions of a negative tone resist which have been exposed to a corresponding energy source become insoluble to a corresponding developer, which will remove the unexposed portions of the negative tone resist.
A photoresist layer is blanket deposited on the substrate surface 606 in step 218 by a resist deposition tool 220. The photoresist is then exposed using the optical mask(s) 222 by an optical lithography tool 224. The exposed portion of the resist layer (as designated by the optical mask(s)) is removed 226 using a resist developing tool 228, and the resulting patterned resist layer is inspected for defects and process control metrology (After Develop Inspection (ADI) and metrology) 230 by an inspection tool 232.
The substrate surface 606 is then blanket modified 234 (using ion implantation), through the pattern expressed in the resist layer by steps 222 and 226, using an ion implantation tool 236 to express (substantially) the same pattern in the underlying material. The resist layer is then removed 238 by a resist removal tool 240. One of ordinary skill in the arts of charged particle beam material modification will understand that other and/or additional steps can be used in a conventional ion implantation process.
Ti represents the amount of time added by a corresponding process step. Yi represents the yield impact of a corresponding process step (one minus probability of introducing one or more yield-reducing defects). Where T is the total time taken by a material modification process, and Y is the expected yield following a material modification process:T=Σi=1NTi  Equation 1:Y=Πi=1NYi  Equation 2:
Numerous steps in conventional semiconductor lithography material modification processes are expensive and time consuming, and potentially introduce defects into the desired pattern, lowering yield. Process-induced defects can be introduced by, for example, wafer handling, resist spin and heating, lithography, resist development, inspection, implantation and thermal processing.